SM5964B
8-Bit Micro-controller
64KB with ISP Flash
& 1KB RAM embedded
EXEN2: Timer 2 external enable bit. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 =
0 causes Timer 2 to ignore events at T2EX.
TR2: Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/
T2
: Timer or counter select for Timer 2. C/
T2
= 0 for timer function. C/
T2
= 1 for external
event counter (falling edge triggered).
CP/
RL2
: Capture/Reload select. CP/
RL2
= 1 causes captures to occur on negative transitions at
T2EX if EXEN2 = 1. CP/
RL2
= 0 causes automatic reloads to occur when Timer 2
overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or
TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
RCLK + TCLK
x
1
0
0
0
7.1
Capture mode
CP/RL2
x
x
1
0
0
Table 7-1 : Timer 2 Operating Modes
TR2
DCEN
Mode
0
x
OFF
1
0
Baud-Rate Generation
1
0
Capture
1
0
Auto-Reload Up-only
1
1
Auto-Reload Up/Down
In the capture mode, there are two options selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit
timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX
causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.
Fosc/12
C/T2=0
T2 pin
C/T2=1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
TR2
Timer2 Interrupt
RCAP2L RCAP2H
Transition
Detector
T2 EX pin
EXF2
EXEN2
Timier2 in Capture Mode
Fig. 7-1： Timer 2 in capture mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M081
Ver A SM5964B 3/7/2014
- 30 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
