欢迎访问ic37.com |
会员登录 免费注册
发布采购

SM5964BW44JP 参数 Datasheet PDF下载

SM5964BW44JP图片预览
型号: SM5964BW44JP
PDF下载: 下载PDF文件 查看货源
内容描述: SM5964B\n8位微控制器\n64KB具有ISP功能的Flash\n和1KB RAM的嵌入式 [SM5964B 8-Bit Micro-controller 64KB with ISP Flash & 1KB RAM embedded]
分类和应用: 微控制器外围集成电路
文件页数/大小: 53 页 / 1710 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
 浏览型号SM5964BW44JP的Datasheet PDF文件第36页浏览型号SM5964BW44JP的Datasheet PDF文件第37页浏览型号SM5964BW44JP的Datasheet PDF文件第38页浏览型号SM5964BW44JP的Datasheet PDF文件第39页浏览型号SM5964BW44JP的Datasheet PDF文件第41页浏览型号SM5964BW44JP的Datasheet PDF文件第42页浏览型号SM5964BW44JP的Datasheet PDF文件第43页浏览型号SM5964BW44JP的Datasheet PDF文件第44页  
SM5964B
8-Bit Micro-controller
64KB with ISP Flash
& 1KB RAM embedded
10. Watch Dog Timer
The Watch Dog Timer (WDT) is an 16-bit free-running counter that generate reset signal if the counter overflows.
The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which
causing software dead loop or runaway. The WDT function can help user software recover from abnormal software
condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be
done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever
un-predicted reset happened. After an external reset the watchdog timer is disabled and all registers are set to
zeros.
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2
~ bit0 (PS[2:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly. As shown in Table 10-1.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter
starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when
overflows. The WDTE bit will be cleared to 0 automatically when SM5964B been reset, either hardware reset or
WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit
counter and let the counter re-start to count from the beginning.
Table 10-1: WDT time-out period
Divider
Time period @ 40MHz
(dividing of Fosc)
8
13.1ms
16
26.21ms
32
52.42ms
64
104.8ms
128
209.71ms
256
419.43ms
512
838.86ms
1024
1677.72ms
Clear
WDTF = 0
WDR
Set WDR = 1
PS[2:0]
000
001
010
011
100
101
110
111
Fosc
1. Power on reset
2. External reset
3. Software write “0”
1
2
PS[2:0]
+
3
PS[2:0]
WDTCLK
WDT
Counter
Enable/Disable
WDT
WDTEN
Refresh
WDT Counter
WDT
time-out
select
WDT time-out
reset
WDTC
CLR
Fig. 10-1: Watchdog timer block diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M081
Ver A SM5964B 3/7/2014
- 40 -