SM5964B
8-Bit Micro-controller
64KB with ISP Flash
& 1KB RAM embedded
12. Pulse Width Modulation (PWM)
There are two PWM channels in SM5964B. The resolution of PWM channel can be 8-bit or 5-bit depending on the
setting on corresponding PBS bit in PWMCn register, where n-0 or 1.
System clock
PWMPS
(2-bit timer)
4
MUX
PWMCLK
PWMTB
(8-bit timer)
COUNT[7:0]
8-bit or 5-bit Logic
Comparator
CMPOUT
PWMOUTn
To P1.2 and P1.3
{ PFS1,PFS0 }
2
( 1 for 5-bit PWM)
PBS
PWMDn[7:5]
PWMDn[4:0]
n=0,1
Figure : PWMn functional block
Mnemonic
P1CON
PWMC0
PWMC1
PWMD0
PWMD1
Description
P1 Control
Register
PWM Control
Register 0
PWM Control
Register 1
PWM Data
Register 0
PWM Data
Register 1
Dir.
9BH
D3H
D4H
B3H
B4H
Bit 7
SDAE
-
-
D0.7
D1.7
Bit 6
SCLE
-
-
D0.6
D1.6
Bit 5
PWM
-
-
-
D0.5
D1.5
Bit 4
-
-
-
D0.4
D1.4
Bit 3
PWM1E
-
-
D0.3
D1.3
Bit 2
PWM0E
PBS
PBS
D0.2
D1.2
Bit 1
-
PFS1
PFS1
D0.1
D1.1
Bit 0
-
PFS0
PFS0
D0.0
D1.0
RST
00H
00H
00H
00H
00H
Mnemonic: P1CON
7
6
SDAE
SCLE
5
-
4
-
3
PWM1E
2
PWM0E
1
-
Address: 9BH
0
Reset
-
00h
PWM1E: Set 1 to configure P1[3] as PWM channel 1 output.
PWM0E: Set 1 to configure P1[2] as PWM channel 0 output.
Mnemonic: PWMC[0:1]
7
6
5
-
-
-
Address: D3h and D4h
1
0
Reset
PFS1
PFS0
00h
4
-
3
-
2
PBS
PBS: When set, the PWM is 5 bits resolution.
PFS [1:0]: The PWM clock divider select.
PFS1
0
0
1
1
PFS0
0
1
0
1
PWM clock divider select
2
4
8
16
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M081
Ver A SM5964B 3/7/2014
- 44 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
