CC1110Fx / CC1111Fx
Bit
7:5
4
BBLOCK
Name
Description
Reserved, write as 0
Boot Block Lock
0
1
3:1
LSIZE[2:0]
Page 0 is write protected
Page 0 is writeable, unless LSIZE is 000
Lock Size. Sets the size of the upper flash area which is write-protected. Byte
sizes are listed below
000
001
010
011
100
101
110
111
32 KB (all pages)
24 KB
16 KB
8 KB
4 KB
2 KB
1 KB
0 bytes (no pages)
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
CC1110F32 and CC1111F32 only
0
DBGLOCK
Debug lock bit
0
1
Disable debug commands
Enable debug commands
Table 44: Flash Lock Protection Bits Definition
12.4 Debug Commands
The debug commands are shown in Table 45.
Some of the debug commands are described
in further detail in the following sections
12.4.1 Debug Configuration
The
commands
and
configuration data byte. The format and
description of this configuration data is shown
in Table 46
12.4.2 Debug Status
A debug status byte is read using the
description of this debug status is shown in
The READ_STATUS command is used e.g.
for polling the status of flash chip erase after a
status required for debug commands HALT,
and STEP_INSTR.
12.4.3 Hardware Breakpoints
The debug command SET_HW_BRKPNT is
used to set a hardware breakpoint. The
CC1110Fx/CC1111Fx
supports up to four hardware
breakpoints. When a hardware breakpoint is
enabled it will compare the CPU address bus
with the breakpoint. When a match occurs, the
CPU is halted.
When issuing the SET_HW_BRKPNT debug
command, the external host must supply three
data bytes that define the hardware
breakpoint. The hardware breakpoint itself
consists of 18 bits while three bits are used for
control purposes. The format of the three data
bytes for the SET_HW_BRKPNT command is
as follows.
The first data byte consists of the following:
Bit
7:5
4:3
2
Description
Unused
Breakpoint number; 0 - 3
Breakpoint enable
0
1
1:0
Disable
Enable
Reserved. Must be 00.
The second data byte consists of bits 15 - 8 of
the hardware breakpoint while the third data
byte consists of bits 7-0 of the hardware
breakpoint. This means that the second and
third data byte sets the CPU CODE address
where the CPU is halted.
SWRS033E
Page 73 of 239
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