C2510Fx / CC2511Fx
again as shown in Figure 37. When 0x00 is
reached, the TIMIF.TxOVFIF flag is set. The
IRCON.TxIF flag is only asserted if the
IEN1.TxEN are set to 1. The up/down mode
can be used when symmetrical output pulses
are required with a period other than 0xFF,
and therefore allows implementation of centre-
aligned PWM output applications.
corresponding
interrupt
mask
bit
TxCTL.OVFIM is set. An interrupt request is
generated when both TxCTL.OVFIM and
TxCC0
0x00
OVFIF = 1
OVFIF = 1
Figure 37: Up/Down Mode
13.9.3 Channel Mode Control
For simple PWM use, output compare modes
3 and 4 are preferred.
The channel mode is set with each channel’s
control and status register TxCCTLn.
13.9.5 Timer 3 and 4 Interrupts
Note: before an I/O pin can be used by the
timer, the required I/O pin must be
configured as a Timer 3/4 peripheral pin as
described in section 13.4.6 on page 64.
There is one interrupt vector assigned to each
of the timers. These are T3 and T4 (interrupt
#11 and #12, see
Table
39).
The
following timer events may generate an
interrupt request:
• Counter reaches terminal count value
(overflow) or turns around on zero /
reach zero
13.9.4 Output Compare Mode
In output compare mode the I/O pin
associated with a channel is set as an output.
After the timer has been started, the contents
of the counter are compared with the contents
of the channel compare register TxCCn. If the
compare register equals the counter contents,
the output pin is set, reset, or toggled
according to the compare output mode setting
of TxCCTLn.CMP. Note that all edges on
output pins are glitch-free when operating in a
given compare output mode. Writing to the
compare register TxCC0 does not take effect
on the output compare value until the counter
value is 0x00. Writing to the compare register
TxCC1takes effect immediately.
• Output compare event
The
register
bits
TIMIF.T3OVFIF,
TIMIF.T3CH0IF,
TIMIF.T4OVFIF,
TIMIF.T3CH1IF, TIMIF.T4CH0IF, and
TIMIF.T4CH1IF contains the interrupt flags
for the two terminal count value event
(overflow), and the four channel compare
events, respectively. These flags will be
asserted regardless off the channel n interrupt
mask bit (TxCCTLn.IM). The CPU interrupt
flag, IRCON.TxIF will only be asserted if one
or more of the channel n interrupt mask bits
are set to 1. An interrupt request is only
generated when the corresponding interrupt
mask bit is set together with IEN1.TxEN. The
interrupt mask bits are T3CCTL0.IM,
T3CCTL1.IM, T4CCTL0.IM, T4CCTL1.IM,
T3CTL.OVFIM, and T4CTL.OVFIM. Note that
enabling an interrupt mask bit will generate a
new interrupt request if the corresponding
interrupt flag is set.
When a compare occurs, the interrupt flag for
the appropriate channel (TIMIF.TxCHnIF) is
asserted. The IRCON.TxIF flag is only
asserted if the corresponding interrupt mask
bit TxCCTLn.IM is set to 1. An interrupt
request is generated if the corresponding
interrupt mask bit is set together with
IEN1.TxEN. When operating in up-down
mode, the interrupt flag for channel 0 is set
when the counter reaches 0x00 instead of
when a compare occurs.
SWRS055D
Page 131 of 243
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