C2510Fx / CC2511Fx
AIN6 - AIN7 inputs (AIN6 must have the
highest input voltage). It is possible to select
the reference voltage as the input to the ADC
in order to perform a conversion of the
reference voltage e.g. for calibration purposes.
Similarly, it is possible to select the ground
terminal GND as an input.
used and CLKCON.CLKSPD should be 000.
The ADC runs on a clock which is the system
clock divided by 6 to give a 4.33/4 MHz ADC
clock. Both the delta-sigma modulator and the
decimation filter use the ADC clock for their
calculations. Using other frequencies will affect
the results, and conversion time. All data
presented within this data sheet assume the
use of the high speed crystal oscillator.
Note: P0_6 and P0_7 do not exist on
CC2511Fx, hence it is not possible to use
external voltage reference for the ADC on
the CC2511Fx.
The time required to perform a conversion
depends on the selected decimation rate.
When, for instance, the decimation rate is set
to 128, the decimation filter uses exactly 128
ADC clock periods to calculate the result.
When a conversion is started, the input
multiplexer is allowed 16 ADC clock periods to
settle in case the channel has been changed
since the previous conversion. The 16 clock
cycles settling time applies to all decimation
rates. This means that the conversion time,
13.10.2.6 ADC Conversion Results
The digital conversion result is represented in
two's complement form. For single ended
configurations the result is always positive (the
result is the difference between ground and the
input signal AINn, where n is 0, 1, 2, …, 7) and
will be a value between 0 and 2047. The
maximum value is reached when the input
amplitude is equal VREF, the selected voltage
reference. For differential configurations the
difference between two pin pairs are converted
and this difference can be negatively signed.
For 12-bit resolution the digital conversion
result is 2047 when the analog input is equal to
VREF, and the conversion result is -2048
when the analog input is equal to -VREF.
T
conv, is given by:
Tconv = (decimation rate + 16) x T where
0.22 µs ≤ T ≤ 0.23 µs for CC2510Fx, depending
on the frequency of the high speed crystal
oscillator
T = 0.25 µs for CC2511Fx
13.10.2.8 ADC Interrupts
The ADC will only generate an interrupt when
an extra conversion has completed.
The digital conversion result is available in
ADCHand ADCLwhen ADCCON1.EOC is set to
1. Note that the conversion result always
resides in MSB section of ADCH:ADCL.
13.10.2.9 ADC DMA Triggers
DMA triggers 20 – 28 are associated with
When reading the ADCCON2.SCH bits, the
number returned will indicate what the last
conversion was. Notice that when the value
written to ADCCON2.SCHis less than 1100, the
number returned will be the number written +
single-ended
or
differential
conversion
sequences (ADCCON2.SCH ≤ 1100). The ADC
will generate a DMA trigger event when a new
sample is ready from a conversion in the
sequence. The same is the case if a single
1.
For example, after a sequence of
conversion is completed (ADCCON2.SCH
≥
conversions from AIN0 to AIN4 has completed,
ADCCON2.SCH will be read as 0101, while
after a single conversion of the temperature
sensor has completed, the register field will be
read as 1110 (same as the value written to it).
If an extra conversion has been initiated by
writing to ADCCON3.ECH, ADCCON2.SCH will
be updated, after the conversion has
completed, with the same value as written to
ADCCON3.ECH, even if this value was less
than 1100.
1100). Be aware that DMA trigger number 27
and 28 are shared with the I2S module.
In addition there is one DMA trigger,
ADC_CHALL, which is active when new data
is ready from any of the conversions in the
ADC conversion sequence and from the single
conversion defined by ADCCON2.SCH.
A
completion of an extra conversion will not
generate a trigger event.
The DMA triggers are listed in Table 51 on
Page 105.
13.10.2.7 ADC Conversion Timing
The high speed crystal oscillator should be
selected as system clock when the ADC is
SWRS055D
Page 142 of 243
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