C2510Fx / CC2511Fx
RFIM (0x91) – RF Interrupt Mask
Bit
7
Name
IM_TXUNF
Reset
0
R/W
R/W
Description
TX underflow
0
1
6
IM_RXOVF
0
R/W
Interrupt disabled
Interrupt enabled
RX overflow
0
1
Interrupt disabled
Interrupt enabled
5
IM_TIMEOUT
0
R/W
RX timeout, no packet has been received in the programmed period.
0
1
Interrupt disabled
Interrupt enabled
4
IM_DONE
0
R/W
Packet received/transmitted. Also used to detect underflow/overflow conditions
0
1
Interrupt disabled
Interrupt enabled
3
IM_CS
0
R/W
Carrier sense
0
1
Interrupt disabled
Interrupt enabled
2
IM_PQT
0
R/W
Preamble quality threshold reached.
0
1
Interrupt disabled
Interrupt enabled
1
IM_CCA
0
R/W
Clear Channel Assessment
0
1
Interrupt disabled
Interrupt enabled
0
IM_SFD
0
R/W
Start of Frame Delimiter, sync word detected
0
1
Interrupt disabled
Interrupt enabled
14.4 TX/RX Data Transfer
Data to transmit is written to the RF Data
register,
RFD.
Received data is read from the
same register. The
RFD
register can be viewed
as a 1 byte FIFO. That means that if a byte is
received in the
RFD
register, and it is not read
before the next byte is received, the radio will
enter RX_OVERFLOW state and the
flag will be set together
with
In TX, the radio will
enter
TX_UNDERFLOW
state
will
be asserted) if too few bytes are written to the
RFD
register compared to what the radio
expect. To exit RX_OVERFLOW and/or
TX_UNDERFLOW state, an SIDLE strobe
command should be issued.
Note: The
RFD
register content will not be
retianed in PM2 and PM3
RX and TX FIFOs can be implemented in
memory and it is recommended to use the
DMA to transfer data between the FIFOs and
the RF Data register,
RFD.
The DMA channel
used to transfer received data to memory
when the radio is in RX mode would have
RFD
as the source (SRCADDR[15:0]), the RX
FIFO
in
memory
as
destination
trigger (TRIG[4:0]). For description on the
usage of DMA, refer to Section 13.5 on Page
A simple example of transmitting data is shown
in Figure 48. This example does not use DMA.
SWRS055D
Page 191 of 243
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