C2510Fx / CC2511Fx
MDMCFG4.
CHANBW_M
00
01
10
11
MDMCFG4.CHANBW_E
00
812
650
541
464
01
406
325
270
232
10
203
162
135
116
11
102
81
68
58
MDMCFG4.
CHANBW_M
00
01
10
11
MDMCFG4.CHANBW_E
00
750
600
500
429
01
375
300
250
214
10
188
150
125
107
11
94
75
63
54
Table 62: Channel Filter Bandwidths [kHz]
(assuming f
ref
= 26 MHz)
Table 63: Channel Filter Bandwidths [kHz]
(assuming f
ref
= 24 MHz)
14.7 Demodulator, Symbol Synchronizer, and Data Decision
CC2510Fx/CC2511Fx
contains an advanced and
highly configurable demodulator. Channel
filtering and frequency offset compensation is
performed digitally. To generate the RSSI level
(see Section 14.10.3 for more information) the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
14.7.1
Frequency Offset Compensation
14.7.2
Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 14.5
on Page 192. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.
14.7.3
Byte Synchronization
When using 2-FSK, GFSK, or MSK
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency, within certain limits, by
estimating the centre of the received data.
This value is available in the
status
register. Writing the value from
into
the
frequency
synthesizer
is
automatically
adjusted
according to the estimated frequency offset.
The tracking range of the algorithm is
selectable as fractions of the channel
bandwidth with the
configuration register.
If the
bit is set,
the offset compensator will freeze until carrier
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
the algorithm.
sets the
gain before the sync word is detected, and
selects the gain after
the sync word has been found.
Byte synchronization is achieved by a
continuous sync word search. The sync word
is a 16 bit configurable field (can be repeated
to get a 32 bit) that is automatically inserted at
the start of the packet by the modulator in
transmit mode. The demodulator uses this
field to find the byte boundaries in the stream
of bits. The sync word will also function as a
system identifier, since only packets with the
correct predefined sync word will be received if
the sync word detection in RX is enabled in
register
MDMCFG2
(see Section 14.10.1). The
sync word detector correlates against the
user-configured 16 or 32 bit sync word. The
correlation threshold can be set to 15/16,
16/16, or 30/32 bits match. The sync word can
be further qualified using the preamble quality
indicator mechanism described below and/or a
carrier sense condition. The sync word is
configured through the
and
registers and is sent MSB first.
In order to make false detections of sync
words less likely, a mechanism called
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
See Section 14.10.2 on Page 198 for more
details.
SWRS055D
Page 193 of 243
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