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TC7106IPL 参数 Datasheet PDF下载

TC7106IPL图片预览
型号: TC7106IPL
PDF下载: 下载PDF文件 查看货源
内容描述: 3-1 / 2位A / D转换器 [3-1/2 DIGIT A/D CONVERTERS]
分类和应用: 转换器光电二极管
文件页数/大小: 19 页 / 296 K
品牌: TELCOM [ TELCOM SEMICONDUCTOR, INC ]
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3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Integrating Capacitor –
C
INT
C
INT
should be selected to maximize the integrator
output voltage swing without causing output saturation. Due
to the TC7106A/7107A superior temperature coefficient
specification, analog common will normally supply the differ-
ential voltage reference. For this case a
±2V
full-scale
integrator output swing is satisfactory. For 3 readings/
second (f
OSC
= 48kHz) a 0.22µF value is suggested. If a
different oscillator frequency is used, C
INT
must be changed
in inverse proportion to maintain the nominal
±2
V integrator
swing.
An exact expression for C
INT
is:
(4000) (
C
INT
=
1
f
OSC
V
INT
Where:
f
OSC
= Clock frequency at Pin 38
V
FS
= Full-scale input voltage
R
INT
= Integrating resistor
V
INT
= Desired full-scale integrator output swing
C
INT
must have low dielectric absorption to minimize
rollover error. A polypropylene capacitor is recommended.
)(
V
FS
)
R
INT
1
Oscillator Components
R
OSC
(Pin 40 to Pin 39) should be 100kΩ. C
OSC
is
selected using the equation:
f
OSC
=
0.45
RC
2
3
4
5
6
7
For f
OSC
of 48kHz, C
OSC
is 100pF nominally.
Note that f
OSC
is divided by four to generate the TC7106A
internal control clock. The backplane drive signal is derived
by dividing f
OSC
by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal-integrate period should be a multiple of 60Hz.
Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 read-
ings/second) will reject both 50Hz and 60Hz.
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Required Full-Scale Voltage*
200.0mV
2.000V
* V
FS
= 2 V
REF
V
REF
100.0mV
1.000V
Integrating Resistor –
R
INT
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current
is 100µA. The integrator and buffer can supply 20µA drive
currents with negligible linearity errors. R
INT
is chosen to
remain in the output stage linear drive region but not so large
that printed circuit board leakage currents induce errors. For
a 200mV full-scale, R
INT
is 47kΩ. 2.0V full-scale requires
470kΩ.
Component
Value
C
AZ
R
INT
C
INT
Note:1.
Nominal Full-Scale Voltage
200.0mV
0.47µF
47kΩ
0.22µF
2.000V
0.047µF
470kΩ
0.22µF
f
OSC
= 48kHz (3 readings/sec)
In some applications a scale factor other than unity may
exist between a transducer output voltage and the required
digital reading. Assume, for example, a pressure transducer
output is 400mV for 2000 lb/in
2
. Rather than dividing the
input voltage by two the reference voltage should be set to
200mV. This permits the transducer input to be used
directly.
The differential reference can also be used when a
digital zero reading is required when V
IN
is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analog common and V
IN
. The transducer output is con-
+
nected between V
IN
and analog common.
The internal voltage reference potential available at
analog common will normally be used to supply the convert-
er's reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
where an externally-generated reference voltage is desired,
refer to Figure 7.
8
TELCOM SEMICONDUCTOR, INC.
3-193