TSC87C52
Pin Configuration
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
VSS1
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA/VPP
ALE/PROG
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.5
P1.6
P1.7
RST
P3.0/RxD
Reserved
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
P2.2/A10
VSS
Reserved
P2.3/A11
P2.4/A12
P3.7/RD
P2.0/A8
P2.1/A9
XTAL2
XTAL1
P1.0/T2
P1.0/T2
1
40
VCC
P1.4
P1.3
P1.2
P0.3/AD3
39
38
37
36
35
6 5 4 3 2 1 44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
Reserved
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
DIP
PLCC/CQPJ
VCC
34
33
32
31
30
29
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34
P1.5
P1.6
P1.7
RST
P3.0/RxD
Reserved
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11
P2.4/A12
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
Reserved
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Flat Pack
P0.3/AD3
28
27
26
25
24
23
P1.0/T2
VSS1
XTAL1
P2.0/A8
VCC
P1.4
P1.3
P1.2
Figure 2 TSC87C52 pin configuration
Do not connect Reserved pins.
MATRA MHS
Rev. C – 10 Sept 1997
VSS
Reserved
P2.2/A10
P3.7/RD
P3.6/WR
P2.1/A9
XTAL2
3
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
