78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-2: ADVANCED TRANSMIT CONTROL REGISTER 1
DFLT
BIT
NAME TYPE
DESCRIPTION
VALUE
0000000 Reserved.
Transmit Fixed Equalizer Enable:
7:1
--
R/W
When enabled, compensates for between 0.75m and 1.5m of FR4 trace
to the serial LVPECL data inputs SIxDP/N
0
TXEQ
R/W
0
0: Normal Operation
1: Enable equalizer
ADDRESS N-3: ADVANCED TRANSMIT CONTROL REGISTER 0
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
10101 Reserved.
7:3
--
R/W
Transmit Driver Amplitude Boost:
Adds roughly 5% or 10% of boost to the CMI output. Limits not tested
during production test.
00 : Normal amplitude
01 : 5% boost
2:1
0
BST[1:0]
FLBK
R/W
R/W
00
0
10 : Reserved
11 : 10% boost
Full Remote (digital) Loopback Enable:
When enabled the recovered receive data is decoded and looped back
to the transmit clock recovery unit exercising the entire receive and
transmit paths.
NOTE: Must be used in conjunction with Serial Plesiochronous Mode or
Serial Loop-Timing Mode.
ADDRESS N-4: MODE CONTROL REGISTER 2
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Line Interface Mode Selection:
0: Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are
disabled. Use RXxP/N and ECLxP/N pins for line interface.
7
CMI
--
R/W
1
1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical
(NRZ) interface disabled. Use RXxP/N and CMIxP/N pins for
line interface.
6:0
R/W XX00000 Reserved.
Page: 14 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
