78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION
LEGEND
TYPE
DESCRIPTION
TYPE DESCRIPTION
Analog Pin
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CMOS Digital Output
A
PO
CO
COZ
OD
S
(Tie unused pins to ground)
CIT
CI
3-State CMOS Digital Input
(Leave unused pins floating)
CMOS Digital Input
CMOS Tristate Digital Output
(Tie unused pins to ground)
(Leave unused pins floating)
Open-drain Digital Output
CIU
CID
CIS
PI
CMOS Digital Input w/ Pull-up
(Leave unused pins floating)
CMOS Digital Input w/ Pull-down
Supply
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
G
Ground
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
TRANSMITTER PINS
NAME
PIN
TYPE DESCRIPTION
PIx0D
PIx1D
PIx2D
PIx3D
31, 66
32, 65
33, 64
34, 63
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
CI
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
PIxCK
30, 67
35, 62
CIS
CO
PTOxCK
Transmit (Serial Mode) Data Input:
SIxDP
SIxDN
10, 87
11, 86
PI
PI
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
Transmit (Serial Mode) Clock Input:
SIxCKP
SIxCKN
7, 90
8, 89
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SIxCKP.
Transmit (Serial Mode) CMI Data Output:
A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse
templates when properly terminated and transformer coupled to 75Ω cable.
Outputs are tri-stated when transmitter is disabled. Active, but undefined
during reset.
CMIxP
CMIxN
121, 104
122, 103
A
Transmit (Serial Mode) Clock Output:
TXxCKP
TXxCKN
124, 101
125, 100
PO
PO
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
Transmit (Serial Mode) LVPECL Data Output:
ECLxP
ECLxN
127, 98
128, 97
Transmit NRZ data outputs used for interfacing with optical transceiver
modules when in Fiber (NRZ) mode.
Page: 16 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
