71M6532D-IGT/F 参数 Datasheet PDF下载

FDS 6531/6532 005

DIO

LCD Segment

Pin number

Configuration (DIO

or LCD segment)

Data Register

–

–

–

–

17

37

13

5

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Data Sheet 71M6531D/F-71M6532D/F

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

28

48

47

0

29

49

24

1

–

–

–

–

–

–

–

–

LCD_MAP[39:32]

–

–

1 –

–

LCD_MAP[55:48]

–

4

5 –

LCD_SEG48[3]

Direction Register

0 = input, 1 = output

DIO_DIR2

(SFR 0xA1)

DIO

LCD Segment

Pin number

Configuration (DIO

or LCD segment)

–

–

–

–

–

–

–

–

–

–

–

–

43

63

29

7

LCD_SEG63[3] LCD_SEG63[0]

44

64

23

0

LCD_SEG64[3] LCD_SEG64[0]

45

65

28

1

LCD_SEG65[3] LCD_SEG65[0]

46

66

5

2

LCD_SEG66[3] LCD_SEG66[0]

–

–

–

–

LCD_BITMAP[63:56] LCD_BITMAP[64:71]

Data Register

–

–

–

–

Direction Register

0 = input, 1 = output

–

–

–

–

1.5.8

Digital I/O – 71M6532D/F

The 71M6532D/F includes up to 43 pins of general-purpose digital I/O. These pins are compatible with 5-

V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:

•

Dedicated DIO pins (4 pins):

o

DIO3

o

DIO56 – DIO58 (3 pins)

•

DIO/LCD segment pins (a total of 37 pins):

o

DIO4/SEG24 – DIO27/SEG47 (24 pins)

o

DIO29/SEG49, DIO30/SEG50 (2 pins)

o

DIO40/SEG60 – DIO45/SEG65 (6 pins)

o

DIO47/SEG67 – DIO51/SEG71 (5 pins)

•

DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX

On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under

MPU control. The pin function can be configured by the I/O RAM registers

LCD_BITMAPn.

Setting

v1.2

© 2005-2009 TERIDIAN Semiconductor Corporation

43

LCD_SEG49[3]

DIO2

=

P2

(SFR 0xA0)

–

–

–

–

1 –

DIO3

=

P3

(SFR 0xB0)