Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
LCD_BITMAPn =
1 configures the pin for LCD, setting
LCD_BITMAPn
= 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the
DIO_DIR
bits
or the
LCD_SEGn
registers. Input and output data are written to or read from the pins using SFR registers
P0, P1,
and
P2.
shows all the DIO pins with their configuration, direction control and data regis-
ters.
Table 40: Data/Direction Registers and Internal Resources for DIO Pins (71M6532D/F)
DIO
LCD Segment
Pin number
Configuration (DIO or
LCD segment)
Data Register
Direction Register
0 = input, 1 = output
Internal Resources
Configurable
DIO
LCD Segment
Pin number
Configuration (DIO or
LCD segment)
Data Register
0
–
PB
–
92
1
–
87
2
–
3
3
–
17
4
24
60
0
5
25
61
1
6
7
8
9
26 27 28 29
62 63 67 68
2
3
4
5
LCD_BITMAP[31:24]
6
7
0
1
6
7
0
1
13 14 15
33 34 35
100
44 29 30
0
1
2
3
LCD_BITMAP[39:32]
2
3
4
5
6
7
DIO1
=
P1
(SFR 0x90)
2
3
4
5
6
7
DIO_DIR1
(SFR 0x91)
Y
Y
–
–
–
–
10
30
69
6
11
31
70
7
12
32
Always DIO
1
2
3
4
5
DIO0
=
P0
(SFR 0x80)
1
2
3
4
5
DIO_DIR0
(SFR 0xA2)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
LCD_SEG49[3]
Direction Register
0 = input, 1 = output
LCD_SEG50[3]
16
17 18 19 20
21
36
37 18 39 40
41
33
12 13 64 65
66
4
5
6
7
0
1
LCD_BITMAP[39:32]
0
1
2
3
4
5
DIO2
=
P2
(SFR 0xA0)
--
1
--
3
4
5
22 23 24 25
42 43 44 45
93 54 46 43
2
3
--
--
LCD_BITMAP[47:40]
6
7
0
1
–
--
--
29 30
--
--
49 50
--
--
32 35
--
1
2
--
LCD_BITMAP[55:48]
2
3
–
5
6
--
DIO3
=
P3
(SFR 0xB0)
26
46
42
--
27
47
41
--
DIO_DIR2
(SFR 0xA1)
--
--
--
--
--
--
DIO
LCD Segment
Pin number
Configuration (DIO or
LCD segment)
40
60
95
41
61
97
42
62
98
43
63
40
44
64
31
0
45
65
38
1
--
--
--
47
67
22
48
68
23
49
69
24
50
70
25
6
51
71
50
7
4
5
6
7
LCD_BITMAP[63:56]
LCD_SEG60[0]
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
--
3
4
5
LCD_BITMAP[71:64]
LCD_SEG67[0]
LCD_SEG68[0]
LCD_SEG69[0]
LCD_SEG64[0]
LCD_SEG65[0]
LCD_SEG70[0]
LCD_SEG70[3]
Data Register
--
LCD_SEG67[3]
LCD_SEG60[0]
LCD_SEG61[0]
LCD_SEG62[0]
LCD_SEG63[0]
LCD_SEG64[3]
LCD_SEG65[3]
LCD_SEG68[3]
LCD_SEG69[3]
Direction Register
0 = input, 1 = output
--
44
© 2005-2009 TERIDIAN Semiconductor Corporation
LCD_SEG71[3]
LCD_SEG71[0]
v1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
