FDS 6531/6532 005
71M6531D/F
71M6532D/F 10 k
Ω
Data Sheet 71M6531D/F-71M6532D/F
V3P3D
10 k
Ω
EEPROM
DIO4
DIO5
SCL
SDA
Figure
32:
I
2
C EEPROM Connection
3.7
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in
and described below:
•
•
•
•
•
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6531.
In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with resistors to prevent operation of the three-wire de-
vice on power-up, before the 71M6531 can establish a stable signal for CS and CLK.
The
DIO_EEX
register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4 and
DIO5 to µWire pins.
The µ-Wire EEPROM interface is only functional when
MPU_DIV[2:0]
= 000.
71M653X
V3P3D
DIO4
DIO5
DIOn
100 kΩ
100 kΩ
10 k
Ω
EEPROM
VCC
CLK
DI
DO
CS
Figure 33: Three-Wire EEPROM Connection
3.8
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ce-
ramic capacitor, as shown in
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
65
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
