FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Description
Name
Location
Reset Wake
Dir
TRIM[7:0]
20FF
0
0
0
0
R/W Contains fuse information, depending on the value written to TRIMSEL[3:0].
R/W Selects the trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
20FD[3:0]
TRIMSEL[3:0]
Trim Fuse
TRIMT[7:0]
Purpose
1
Trim for the magnitude of VREF
–
–
–
–
VERSION[7:0]
2006
20C8
R
R
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0]
Silicon Version
0001 0101
A05
VREF_CAL
VREF_DIS
WAKE_ARM
2004[7]
2004[3]
20A9[7]
0
0
0
0
0
–
R/W Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
R/W Disables the internal voltage reference.
Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it
with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset
and disarmed whenever the IC is in MISSION or BROWNOUT mode. The timer must
be armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is com-
manded.
W
–
–
0
WAKE_PRD
WAKE_RES
20A9[2:0]
20A9[3]
20B1[0]
001
0
R/W Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maximum value is 7.
R/W Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
–
R/W This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD_RST
SFR F8[7]
2002[2]
0
0
0
0
W
WD timer bit. This bit must be accessed with byte operations. Operations possible for
this bit are: Write 0xFF: Resets the WDT.
The WD overflow status bit. This bit is set when the WD timer overflows. It is powered
by the nonvolatile supply and at bootup will indicate if the part is recovering from a WD
overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
WD_OVF
R/W
–
0
–
0
An 8-bit value has to be written to this address prior to accessing the RTC registers.
WE
201F[7:0]
SFR B2[5]
W
WRPROT_BT
When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page
erase.
WRPROT_CE
SFR B2[4]
0
0
When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory
from flash page erase.
v1.2
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