FDS 6531/6532 005
•
•
•
Data Sheet 71M6531D/F-71M6532D/F
Apply proper values to
SLOTn_SEL
and
SLOTn_ALTSEL.
Set
CHOP_E
= 00.
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see
This means that
the product of the number of cycles per frame and the number of conversions per frame must be 12 (al-
lowing for one settling cycle).
During operation,
CHOP_E
= 00 enables the automatic chopping mode and forces an alternate multiplex-
er sequence at regular intervals. This enables accurate temperature measurement.
4.3.5
CE Calculations
Table 50: CE
EQU
Equations and Element Input Mapping
Element Input Mapping
W0SUM/
VAR0SUM
VA*IA
VA*(IA-IB)/2
VA*IA
W1SUM/
VAR1SUM
VA*IB
(VA * IB)/2
VB*IB
I0SQSUM
IA
IA-IB
IA
I1SQSUM
IB
IB
IB
EQU
Watt & VAR Formula
(WSUM/VARSUM)
VA IA (1 element, 2W 1
φ
)
with tamper detection
VA*(IA-IB)/2
(1 element, 3W 1
φ
)
VA*IA + VB*IB
(2 element, 4W 2
φ
)
0
1
2
4.3.6
CE Status and Control
The
CESTATUS
register provides information about the status of voltage and input AC signal frequency,
which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It con-
tains sag warning flags for VA and VB as well as F
0
, the derived clock operating at the fundamental input
frequency.
CESTATUS
represents the status flags for the preceding CE code pass (CE busy interrupt).
Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at
every CE_BUSY interrupt. The significance of the bits in
CESTATUS
is shown in
CE Address
0x80
Name
CESTATUS
Description
See description of
CESTATUS
bits in
Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation
required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to gen-
erate interrupts when a sag occurs (see the description of the
CECONFIG
register)
Table 51:
CESTATUS
Bit Definitions
CESTATUS
[bit]
31:29
28
27
26
25
24:0
Name
Not Used
F0
Reserved
SAG_B
SAG_A
Not Used
Description
These unused bits will always be zero.
F0
is a square wave at the exact fundamental input frequency.
Normally zero. Becomes one when VB remains below
SAG_THR
for
SAG_CNT
samples. Will not return to zero until VB rises above
SAG_THR.
Normally zero. Becomes one when VA remains below
SAG_THR
for
SAG_CNT
samples. Will not return to zero until VA rises above
SAG_THR.
These unused bits will always be zero.
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