DS_8024RN_020
73S8024RN Data Sheet
2 System Controller Interface
Three separated digital inputs allow direct control of the card interface from the host as follows:
•
•
•
Pin
CMDVCC:
When low, starts an activation sequence.
Pin RSTIN: controls the card Reset signal (when enabled by the sequencer).
Pin 5V/#V: Defines the card voltage.
Card clock is controlled by four digital inputs:
•
•
•
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock
frequency (crystal or external clock).
CLKSTOP (active high) allows card power down mode by stopping the card clock.
CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the
OFF
pin informs the host about the
card presence only (Low = No card in the reader). When
CMDVCC
is set low (Card activation sequence
requested from the host), low level on
OFF
means a fault has been detected (e.g. card removal during
card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation
sequence.
Rev. 1.8
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
