78Q2123/78Q2133
MicroPHY™
10/100BASE-TX Transceiver
REGISTER DESCRIPTION
The 78Q2123/78Q2133 implement 13 16-bit registers, which are accessible via the MDIO and MDC pins. The
supported registers are shown below in the following table. Attempts to read unsupported registers will be
ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the
registers except those that are unique to the 78Q2123/78Q2133 will respond to the broadcast PHYAD value of
‘00000’. The registers specific to the 78Q2123/78Q2133 occupy address space MR16-24.
ADDRESS
0
1
2
3
4
5
6
7
8-14
15
16
17
18
19
20-22
23
24
Legend:
TYPE
R
WC
0/1
DESCRIPTION
Readable by management.
Writeable by management. Self
Clearing.
Default value upon power up or
reset
TYPE DESCRIPTION
W
Writeable by management.
RC
Readable by management.
Cleared upon a read operation.
SYMBOL
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
MR8-14
MR15
MR16
MR17
MR18
MR19
MR20-22
MR23
MR24
NAME
Control
Status
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Not Implemented
Reserved
Not Implemented
Vendor Specific
Interrupt Control/Status Register
Diagnostic Register
Transceiver Control
Reserved
LED Configuration Register
MDI/MDIX Control Register
DEFAULT (HEX)
(3100)
(7849)
000E
7237
(01E1)
0000
0000
0000
0000
0000
(0140)
0000
0000
4XXX
0000
0010
(00C0)
Page: 11 of 42
©
2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
