CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
t
c
From Output
Under Test
Duty Cycle
C
L
500 Ω
(see Note A)
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
t
t
f
r
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
V
OH
1.5 V
CPU Clock
GND
(PCLK)
V
OH
1.5 V
CPU Clock
(PCLK)
GND
skew
skew
offset
PCLK-to-PCLK Skew
V
OH
1.5 V
PCI Clock
(BCLK)
GND
V
OH
1.5 V
PCI Clock
(BCLK)
GND
BCLK-to-BCLK Skew
V
OH
1.5 V
CPU Clock
(PCLK)
GND
V
OH
1.5 V
PCI Clock
(BCLK)
GND
offset
PCLK-to-BCLK Offset
Figure 2. Waveforms for Calculation of t
and Offset
skew
7
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