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SBAS451 – OCTOBER 2008
SYSTEM CLOCK INPUT
The PCM1789 requires an external system clock input applied at the SCKI input for DAC operation. The system
clock operates at an integer multiple of the sampling frequency, or f
S
. The multiples supported in DAC operation
include 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
, and 1152 f
S
. Details for these system clock multiples are
shown in
and
show the SCKI timing requirements.
Table 1. System Clock Frequencies for Common Audio Sampling Rates
DEFAULT
SAMPLING
MODE
SAMPLING
FREQUENCY, f
S
(kHz)
8
16
Single rate
32
44.1
48
Dual rate
Quad rate
88.2
96
176.4
192
SYSTEM CLOCK FREQUENCY (MHz)
128 f
S
N/A
2.0480
4.0960
5.6448
6.1440
11.2896
12.2880
22.5792
24.5760
t
SCH
High
System Clock
(SCKI)
Low
t
SCL
t
SCY
0.8 V
2.0 V
192 f
S
N/A
3.0720
6.1440
8.4672
9.2160
16.9344
18.4320
33.8688
36.8640
256 f
S
2.0480
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
N/A
384 f
S
3.0720
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
512 f
S
4.0960
8.1920
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
768 f
S
6.1440
12.2880
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
1152 f
S
9.2160
18.4320
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
Figure 18. System Clock Timing Diagram
Table 2. Timing Requirements for
SYMBOL
t
SCY
t
SCH
t
SCL
—
PARAMETER
System clock cycle time
System clock width high
System clock width low
System clock duty cycle
MIN
27
10
10
40
60
MAX
UNIT
ns
ns
ns
%
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