ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
IEEE 1149.1 JTAG compatibility statement
The TMS320C6414T/15T/16T DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be released only
in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions
work correctly independant of current state of RESET.
For maximum reliability, the TMS320C6414T/15T/16T DSP includes an internal pulldown (IPD) on the TRST
pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will
always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However,
some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive
TRST high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1
and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For
more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the C6414T, C6415T, C6416T GLZ BSDL file contains information
and constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6414T/15T/16T JTAG emulation, see the TMS320C6000 DSP Designing
for JTAG Emulation Reference Guide (literature number SPRU641).
EMIF device speed
The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM
interface when in a system that meets the following requirements:
−
−
−
−
−
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
166-MHz SDRAM for 133-MHz operation (applies only to EMIFA)
143-MHz SDRAM for 100-MHz operation
Timing analysis must be done to verify all AC timings are met for all configurations. Verification of AC timings
is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer
information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
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