TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
Tester Pin Electronics
Data Sheet Timing Reference Point
42
W
3.5 nH
Transmission Line
Z0 = 50
W
(see note)
Output
Under
Test
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 12. Test Load Circuit for AC Timing Measurements
The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate
the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks, V
OL
MAX
and V
OH
MIN for output clocks, V
ILP
MAX and V
IHP
MIN for PCI input clocks, and V
OLP
MAX and V
OHP
MIN for
PCI output clocks.
Vref = VIH MIN (or VOH MIN or
VIHP MIN or VOHP MIN)
Vref = VIL MAX (or VOL MAX or
VILP MAX or VOLP MAX)
Figure 14. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
78
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
