UC1914
UC2914
UC3914
APPLICATION INFORMATION (cont.)
UDG-97055
t0:
Normal conditions - output current is nominal, output
voltage is at positive rail, VCC
t1:
Fault control reached - output current rises above the
programmed fault value, C
T
begins to charge with
≅
100µA + I
PL
.
t2:
Maximum current reached - output current reaches
the programmed maximum level and becomes a con-
stant current with value IMAX.
t3:
Fault occurs - C
T
has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current to
flow, VOUT discharge to GND.
t4:
Reset comparator threshold reached but no retry
since LR pin held high.
t5:
LR toggled low, NMOS turned on and sources cur-
rent to load.
t6 = t3
t7:
LR toggled low before V
CT
reaches reset compara-
tor threshold, causing retry.
t8:
Since LR toggled low during present cycle, NMOS
turned on and sources current to load.
t9 = t0:
Fault released, normal condition - return to
normal operation of the hot swap power manager.
Figure 3b. Typical timing diagram utilizing LR (Latch Reset) function.
9
TI [ TEXAS INSTRUMENTS ]
