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Preliminary T4312816A
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
0
1
(Burst of Four)
Starting Address
(column address A1-A0 binary)
0,1
1,0
0,1
1,0
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0 binary)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
000
001
010
011
100
101
110
111
8Mx16 divice.
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 for
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain CKE = ‘H’ , L(U)DQM = ‘H’ and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initalize the mode register.
Cf.) Sequence of 4 & 5 is regardless of the order.
TM Technology Inc. reserves the right
P.11
to change products or specifications without notice.
Publication Date:APR. 2003
Revision: 0.B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
