tm
PIN
CLK
TE
CH
Preliminary T4312816A
PIN DESCRIPTION
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CS
CKE
Clock Enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A11
BA0 ~ BA1
Address
Bank Select Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
RAS
Row Address Strobe
with
RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
CAS
Column Address Strobe
with
CAS
low.
Enables column access .
WE
L(U)DQM
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
Write Enable
Data Input/Output
Mask
Data Input/Output
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Data Output
Power/Ground
No
Connection/Reserved
for Future Use
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
N.C/RFU
TM Technology Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: APR. 2003
Revision: 0.B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
