TE
tmCH
T431616D/E
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
Burst Stop
don't care
NOP
NOP
CAS# latency=1, 2, 3
DQ's
DIN A
DIN
A
DIN A
2
1
0
Input data for the Write is masked.
Termination of a Burst Write Operation
(Burst Length = X, CAS# Latency = 1, 2, 3)
10 Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address
inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation
command.
11 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-
before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each
time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address
bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on
every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The
time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh
command, both banks need to be in the idle state and the device must not be in power down mode (CKE is high
in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed.
The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed.
12 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data
retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM
become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is
internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an
indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on
CKE (SelfRefresh Exit command).
13 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device
Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank
currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a
burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh
mode.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 15
Publication Date: FEB. 2007
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
