tm
Register
Refresh
TE
CH
T436416A
SIMPLIFIED TRUTH TABLE
COMMAND
BA
A
10
/AP A
9
~A
0,
Note
CKEn-1 CKEn
CS
RAS
CAS
WE DQM
A11
0,1
Mode Register Set
H
X
L
L
L
L
X
X
1,2
Auto Refresh
Self
Refresh
Entry
Exit
H
L
H
H
H
H
H
H
L
H
L
H
H
H
X
H
L
H
X
X
X
X
X
L
H
L
H
L
L
H
L
L
L
L
L
H
L
X
H
L
H
L
L
H
X
L
H
H
H
L
X
V
X
X
H
X
V
X
L
H
X
H
L
L
H
H
X
V
X
X
H
X
V
H
H
X
H
H
L
L
L
X
V
X
X
H
X
V
X
X
X
X
X
X
X
X
X
X
X
X
V
X
7
V
X
L
H
X
V
V
V
X
X
Row Address
L
H
L
H
X
Column
Address
(A0~A7)
Column
Address
(A0~A7)
3
3
Bank Active & Row Address
Auto Precharge Disable
Read Column
Auto Precharge Enable
Address
Write & Column
Auto Precharge Disable
Auto Precharge Enable
Address
Burst Stop
4,5
4,5
6
4
Precharge
Bank Selection
Both Banks
Entry
Exit
Entry
Clock Suspend or
Active Power Down
Precharge Power Down
Mode
DQM
No Operation Command
Exit
H
X
X
X
X
X
L
H
H
H
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A
0
~A
11
, BA0~BA1 : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA0~BA1 : Bank select address.
If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.
If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.
If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.
If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected
If A
10
/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at
t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TM Technology Inc. reserves the right
P.12
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
