Transcend 44-Pi
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Transcend 44-P n DE F ash Modu e
TS128M ~ 8GDOM44V-S
TS128M ~ 8GDOM44V-S
True IDE Multiword DMA Mode Read/Write Timing Diagram
Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram
Notes:
(1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the
time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the
signal at a later time to continue the DMA operation.
(2) This signal may be negated by the host to suspend the DMA transfer in progress.
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