TS2GDOM44H-S 参数 Datasheet PDF下载

Transcend 44-Pi

i

n I

I

DE Fl

l

ash Modul

l

e (Hori

i

zontal

l

)

Transcend 44-P n DE F ash Modu e (Hor zonta )

TS128M ~ 4GDOM44H-S

TS128M ~ 4GDOM44H-S

Ultra DMA Mode Read/Write Timing Specification

Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA,

commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword

DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data

burst only. When this protocol is used there are no changes to other elements of the ATA protocol.

TRUE IDE MODE

UDMA

DMARQ

-DMACK

STOP

1

-HDMARDY

1,2

HSTROBE(W)

1,3,4

-DDMARDY(W)

1,3

DSTROBE(R)

1,2,4

D[15:00]

A[02:00]

5

-CSEL

INTRQ

-CS0

-CS1

UDMA Signal

DMARQ

DMACK

STOP

HDMARDY(R)

HSTROBE(W)

DDMARDY(W)

DSTROBE(R)

DATA

ADDRESS

CSEL

INTRQ

Card Select

Type

Output

Input

Input

Input

Output

Bidir

Input

input

Output

Input

Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.

2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.

3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.

4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.

5) Address lines 03 through 10 are not used in True IDE mode.

Several signal lines are redefined to provide different functions during an Ultra DMA data burst.

These lines assume their UDMA definitions when:

1. An Ultra DMA mode is selected, and

2. A host issues a READ DMA, or a WRITE DMA command requiring data transfer, and

3. The device asserts (-)DMARQ, and

4. The host asserts (-)DMACK.

These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation

of -DMACK by the host at the termination of an Ultra DMA data burst.

With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the

same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data

strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra

Transcend Information Inc.

10

Ver 1.0