Transcend 44-Pi
i
n I
I
DE Fl
l
ash Modul
l
e (Hori
i
zontal
l
)
Transcend 44-P n DE F ash Modu e (Hor zonta )
TS128M ~ 4GDOM44H-S
TS128M ~ 4GDOM44H-S
True IDE Multiword DMA Mode Read/Write Timing Specification
Item
Mode 0
(ns)
480
215
150
5
100
20
0
20
50
215
120
40
50
15
20
Mode 1
(ns)
150
80
60
5
30
15
0
5
50
50
40
40
30
10
25
Mode 2
(ns)
120
70
50
5
20
10
0
5
25
25
35
35
25
10
25
Mode 3
(ns)
100
65
50
5
15
5
0
5
25
25
35
35
10
10
25
Mode 4
(ns)
80
55
45
5
10
5
0
5
20
20
35
35
5
10
25
t
0
t
D
t
E
t
F
t
G
t
H
t
I
t
J
t
KR
t
KW
t
LR
t
LW
t
M
t
N
t
Z
Notes:
Cycle time (min)
1
-IORD / -IOWR asserted width(min)
1
-IORD data access (max)
-IORD data hold (min)
-IORD/-IOWR data setup (min)
-IOWR data hold (min)
DMACK to –IORD/-IOWR setup (min)
-IORD / -IOWR to -DMACK hold (min)
-IORD negated width (min)
1
-IOWR negated width (min)
1
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CS(1:0) valid to –IORD / -IOWR
CS(1:0) hold
-DMACK
(1) t
0
is the minimum total cycle time and t
D
is the minimum command active time, while t
KR
and t
KW
are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive time.
The three timing requirements of t
0
, t
D
, t
KR
, and t
KW
shall be met. The minimum total cycle time requirement
is greater than the sum of t
D
and t
KR
or t
KW
.for input and output cycles respectively. This means a host
implementation can lengthen either or both of t
D
and either of t
KR
, and t
KW
as needed to ensure that t
0
is
equal to or greater than the value reported in the device’s identify device data.
Transcend Information Inc.
8
Ver 1.0
TRANSCEND [ TRANSCEND INFORMATION. INC. ]
