TQS Reliability Report # 00-08
TQ8223 Device Product Qualification
Reliability Test Report
08/01/00
Process Description
TriQuint’ QEDA2 process is a Gallium Arsenide (GaAs) semiconductor process fabricated at TriQuint’
s
s
Hillsboro, Oregon facility
Product Description
The TQ8223 is a TriQuint standard product, which is similar to the SC5068. Both parts are identical except
for added circuitry in the SC5068 containing key customer intellectual property. The SC5068 was chosen to
qualify both parts since it is a superset of the TQ8223.
The TQ8223 and SC5068 are multi-configuration SONET/SDH OC48/STM16 CDR/DEMUX that
regenerate and re-time serial 2.48832 Gb/s data. They recover the 2.48832 GHz clock from the data
stream and frequency divide it to generate control signals and clocks used to perform the demultiplexing
function.
The TQ8223 and SC5068 operate in one of three different time-division demultiplexing modes, making it
extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream can
be demultiplexed into either an 8-bit wide 311.04 MHz TTL data bus, a 16-bit wide 155.52 MHz TTL data
bus, or a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also available. The device
generates byte-wise parity check bits for the demultiplexed data and provides associated clock outputs for
the different modes. Parity checking is not required for normal device operation.
The TQ8223 and SC5068 provide added flexibility through a selectable internal/external Voltage Controlled
Oscillator (VCO) as well as a selectable internal Phase Locked Loop (PLL). If an external high frequency
clock is utilized, a single-ended or differential AC coupled clock may be used. The internal PLL contains a
NRZ phase detector which enables it to adjust the phase of the internal clock such that sampling of the
incoming data stream occurs in the middle of the data eye. An offset control allows adjustment of 128pS
around this nominal position.
Operating from a single +5V supply, the TQ8223 and SC5068 are fully compliant with SONET/SDH jitter
tolerance and transfer specifications. A TTL level LOCK signal is supplied to indicate when the frequency
difference between the internal 38.88 MHz clock and the external 38.88 MHz clock is less than 488 ppm.
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