W78LE54C/W78L054C
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
×
2
14
×
PRESCALER
×
1000
×
12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL
IDLE
EXTERNAL
RESET
14-BIT TIMER
CLEAR
OSC
1/12
PRESCALER
INTERNAL
RESET
Watchdog Timer Block Diagram
CLRW
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
19.66 mS
39.32 mS
78.64 mS
157.28 ms
314.57 mS
629.14 mS
1.25 S
2.50 S
-8-
TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
