UTC571
THD TRIM
8.9
LI
NEAR I
NTEGRATED CI
RCUI
T
R3
6.11
R3
20K
R2
20K
BASIC CIRCUIT HOOK-UP AND OPERATION
INV
IN
5.12
G
IN
3.14
G
R4
30K
VREE
1.8V
7.10
OUTPUT
IG
R1
10K
RECT
IN
2.15
V
CC
PIN 13
GND PIN 4
1.16
C
RECT
Figure 2. Chip Block Diagram
Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-
wave averaging rectifier provides a gain control current, I
G
, for the variable gain
(∆G)
cell. The output of the DG
cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish
circuit gain and set the output DC bias.
The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V
reference denoted V
REF
. The non-inverting input of the op amp is tied to V
REF
, and the
summing nodes
of the
rectifier and
∆G
cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the V
REF
potential.
R3
C
IN1
R2
G
V
OUT
V
IN
C
IN2
R1
R4
V
REF
NOTE: GAIN= 2R
3
V
IN
(avg)
R
1
R
2
I
B
I
B
=140A
C
RECT
Figure 3. Basic Expander
Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, V
IN
is applied to the inputs
of both the rectifier and the
∆G
cell. When the input signal drops by 6dB, the gain control current will drop by a
factor of 2, and so the gain will drop 6dB. The output level at V
OUT
will thus drop 12dB, giving us the desired 2 to 1
expansion.
YOUW ANG ELECTRONI CO.
CS
LTD
6
UTC-IC [ UNISONIC TECHNOLOGIES ]
