UTC571
LI
NEAR I
NTEGRATED CI
RCUI
T
At very low input signal levels the bias current of Q 2 , (typically 50nA), will become significant as it must be
supplied by Q 5 . Another low level error can be caused by DC coupling into the rectifier. If an offset voltage exists
between the V IN input pin and the base of Q 2 , an error current of V
OS
/R 1 will be generated. A mere 1mV of
offset will cause an input current of 100nA which will produce twice the error of the input bias current. For highest
accuracy, the rectifier should be coupled into capacitively. At high input levels the
β
of the PNP Q 6 will begin to
suffer, and there will be an increasing error until the circuit saturates. Saturation can be avoided by limiting the
current into the rectifier input to 250mA. If necessary, an external resistor may be placed in series with R 1 to limit
the current to this value. Figure 7 shows the rectifier accuracy vs input level at a frequency of 1kHz.
ERROR GAIN dBm
+1
0
-1
-40
-20
0
RECTIFIER INPUT dBm
Figure 7. Rectifier Accuracy
At very high frequencies, the response of the rectifier will fall off. The roll-off will be more pronounced at lower
input levels due to the increasing amount of gain required to switch between Q 5 or Q 6 conducting. The rectifier
frequency response for input levels of 0dBm, -20dBm, and -40dBm is shown in Figure 8. The response at all three
levels is flat to well above the audio range.
GAIN ERROR (dB)
INPUT=0dBm
0
-40dBm
-20dBm
3
10K
FREQUENCY(Hz)
1MEG
Figure 8. Simplified
∆G
Cell Schematic
YOUW ANG ELECTRONI CO.
CS
LTD
9
UTC-IC [ UNISONIC TECHNOLOGIES ]
