VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
Data Sheet
VSC8061/VSC8062
VSC8061 Phase Detector Logic Diagram
The internal phase detector of the VSC8061 compares the phase difference between the internally gener-
ated divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in
phase, the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses
with pulse widths proportional to the phase difference will be present at the U output. Conversely, if DCLK pre-
cedes CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D
output. The other output will remain low. The Phase Detector ignores phase differences for falling edges. This
circuitry is useful for implementing a Clock Multiplier Unit (CMU) function with the VSC8061. For example,
the DLCK can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator
(VCO) at 16x the frequency of the reference clock can be used as the CLK input for the VSC8061. The phase
detector outputs (U and D) can then be used by an external integrator to generate an output that controls the
VCO. The generated 16x clock from the VCO will be phase-locked to the reference clock.
Figure 4: VSC8061 Phase Detector Logic Diagram
CLK16
R Q
S
S
R Q
DCLK
U
D
Figure 5: Phase Detector Input and Output Waveforms
CLK16
DCLK
U
D
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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G52069-0, Rev 4.3
05/11/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
