VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
VSC8111
Figure 10:Transmit High Speed Data Timing Diagram
TTXCLK
TXCLKOUT-
TXCLKOUT+
TSKEW
TSKEW
TXDATAOUT+
TXDATAOUT-
Table 10:Transmit High Speed Data Timing Table (STS-12 Operation)
Parameter
Description
Min
Typ
Max
Units
T
Transmit clock period
-
1.608
-
ns
TXCLK
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
T
-
-
250
ps
SKEW
Table 11:Transmit High Speed Data Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
T
Transmit clock period
-
6.43
-
ns
TXCLK
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
T
-
-
250
ps
SKEW
Data Latency
The VSC8111 contains several operating modes, each of which exercise different logic paths through the
part. Table 12 bounds the data latency through each path with an associated clock signal.
Table 12: Data Latency
Clock
Reference
Range of
Clock cycles
Circuit Mode
Description
Transmit
Receive
Data TXIN [7:0] to MSB at TXDATAOUT
MSB at RXDATAIN to data on RXOUT [7:0]
TXCLKOUT
RXCLKIN
4-13
24-32
Equipment
Loopback
Byte data TXIN [7:0] to byte data on RXOUT [7:0]
MSB at RXDATAIN to MSB at TXDATAOUT
TXCLKOUT
RXCLKIN
27-35
2
Facilities
Loopback
G52142-0, Rev 4.2
8/31/98
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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