VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Figure 9: Receive Data Output Timing Diagram
Data Sheet
VSC8111
T
RXCLKIN
RXCLKIN+
RXCLKIN-
T
RXLSCK
RXLSCKOUT
RXOUT [7:0]
A1
A2
A2
A2
A2
T
RXVALID
FP
Table 8: Receive Data Output Timing Table
(STS-12
Operation)
Parameter
T
RXCLKIN
T
RXLSCK
T
RXVALID
T
PW
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
Description
Min
-
-
4.0
-
Typ
1.608
12.86
-
12.86
Max
-
-
-
-
Units
ns
ns
ns
ns
Table 9: Receive Data Output Timing Table
(STS-3
Operation)
Parameter
T
RXCLKIN
T
RXLSCKT
T
RXVALID
T
PW
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
Description
Min
-
-
22
-
Typ
6.43
51.44
-
51.44
Max
-
-
-
-
Units
ns
ns
ns
ns
Page 10
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
