VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Loop Timing
Data Sheet
VSC8111
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
LOOPTIM1 mode bypasses the REFCLK input and uses the divide-by-8 version of the receive clock as the
reference input to the CMU. This mode is selected by asserting the LOOPTIM1 input high. The part is forced
out of this mode if it is in the Loss of Signal state or in Equipment Loopback to prevent the CMU from feeding
its own clock back. The user needs to set the B[0:2] inputs to select 78MHz operation to match the RXLSCK-
OUT frequency.
Clock Multiplier Unit
The VSC8111 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (select pins B0-B2
select divide-by ratios of 8, 12, 16 and 32, see Table 2) and the reference clock. The integrator provides a trans-
fer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-
cated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter
generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke
(
π
filter) on the (VDDANA) power pins. Note: Vitesse recommends a (
π
filter) C-L-C choke over using a ferrite
bead. All ground planes should be tied together using multiple vias.
Table 1: Recommended External Capacitor Values
Reference
Frequency
[MHz]
19.44
38.88
51.84
77.76
Divide Ratio
32
16
12
8
CP
0.1
0.1
0.1
0.1
CN
0.1
0.1
0.1
0.1
Type
X7R
X7R
X7R
X7R
Size
0603/0803
0603/0803
0603/0803
0603/0803
Tol.
+/-10%
+/-10%
+/-10%
+/-10%
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
