VSC8114QB 参数 Datasheet PDF下载

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Figure 7: Jitter Tolerance

Data Sheet

VSC8114

J

ITTER

(UI

P

-

P

)

150

Bellcore Requirement

60

VSC8114 Guaranteed

Jitter Tolerance

15

6

1.5

0.6

0.15

10

30

300

25

K

250

K

2.5M

J

ITTER

F

REQ

(H

Z

)

Data Latency

The VSC8114 contains several operating modes, each of which exercise different logic paths through the

part. Table 2 bounds the data latency through each path with an associated clock signal.

Table 2: Data Latency

Circuit Mode

Receive

Facilities

Loopback

Description

MSB at RXDATAIN to data on RXOUT [7:0]

MSB at RXDATAIN to MSB at TXDATAOUT

Clock

Reference

RXCLKIN

RXCLKIN

Range of Clock

cycles

25-35

2-4

Page 8

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VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52185-0, Rev 4.0

11/1/99