VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b
a
b
Single
Ended
Swing
=
α
Differential
Swing
a
* Differential swing
(α)
is specified as | b - a | ( or | a - b | ), as is the single ended swing.
Differential swing is specified as equal in magnitude to single ended swing.
=
α
Table 1: AC Characteristics
Parameters
t
pdd
t
pd32
t
DR
, t
DF
t
CLKR
, t
CLKF
CLK16O
D
Description
Data valid from falling
edge of CLK16O+
CLK32O transition from
falling edge of CLK16O+
D[15:0]+/- rise and fall
times
CLK16O+/- rise and fall
times
CLK16O+/- duty cycle
distortion
DI+ setup time with respect
to falling edge of
HSCLKI+
DI+ hold time with respect
to falling edge of
HSCLKI+
HSCLKI+/- duty cycle
distortion
Min
0
0
Max
800
1.0
400
250
Units
ps.
ns.
ps
ps
% of
clock
cycle
ps
Conditions
—
—
45
20% to 80% into 50 Ohm load.
See Figure 7
20% to 80% into 50 Ohm load.
See Figure 7
High speed clock input at 2.488GHz
55
t
dsu
t
dh
100
—
75
—
ps
% of
clock
cycle
HSCLKI
D
40
60
G52239-0, Rev. 3.3
5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
