VIS
AC Characteristics
(
T
a
= 0 to + 70
°C
, V
cc
= 5V
±
10
% or 3.3V
±
10
%, V
ss
= 0V) *1, *2, *3, *4, *5
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Test conditions
• Output load: two TTL Loads and 50pF (V
CC
= 5.0V
±
10
%)
one TTL Load and 50pF (V
CC
= 3.3V
±
10
%)
• Input timing reference levels:
V
IH
= 2.4V, V
IL
= 0.8V (V
CC
= 5.0V
±
10
%); V
IH
= 2.0V, V
IL
= 0.8V (V
CC
= 3.3V
±
10
%)
• Output timing reference levels:
V
OH
= 2.0V, V
OL
= 0.8V (V
CC
= 5V
±
10
%, 3.3V
±
10
%)
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
VG26(V)(S) 18165C
-5
Parameter
Random read or write cycle time
RAS precharge time
LCAS / UCAS precharge time in normal
mode
RAS pulse width
LCAS / UCAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to LCAS / UCAS delay time
RAS to column address delay time
Column address to RAS lead time
RAS hold time
LCAS / UCAS hold time
LCAS / UCAS to RAS precharge time
OE to Din delay time
Transition time (rise and fall)
Refresh period
Refresh period (S- Version)
LCAS / UCAS to output in Low- Z
LCAS / UCAS delay time from Din
OE delay time from Din
Document:1G5-0147
Unit
Notes
-6
Max
-
-
-
Min
104
40
10
Max
-
-
-
ns
ns
ns
Symbol
t
RC
t
RP
t
CPN
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RAL
t
RSH
t
CSH
t
CRP
t
OED
t
T
t
REF
t
REF
t
CLZ
t
DZC
t
DZO
Min
84
30
10
50
8
0
8
0
8
12
10
25
8
38
5
12
1
-
-
0
0
0
Rev.1
10000
10000
-
-
-
-
37
25
-
-
-
-
-
50
16
128
-
-
-
60
10
0
10
0
10
14
12
30
10
40
5
15
1
-
-
0
0
0
10000
10000
-
-
-
-
45
30
-
-
-
-
-
50
16
128
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
6
7
8
9
10
11
12
Page 10
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