VIS
Capacitance
(Ta=25°C,f=1MHZ)
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Parameter
Input capacitance(CLK)
Input capacitance(all input pins except data
pins)
Data input/output capacitance
Symbol
C
11
C
12
C
I/O
Typ
2.5
2.5
4.0
Max
4
5
6.5
Unit
pF
pF
pF
Recommended D.C. Operating Conditions (V
DD
= 3.3V
Description/test condition
Operating Current
t
≥
t
, Outputs Open
RC RC
(
min
)
Address changed once during t
CK(min)
.
Burst Length = 1 (One Bank Active)
Precharge Standby Current in non power-down mode
t
CK
= t
CK(min)
,
CS
≥
V
I H
(min)
, CKE
≥
V
I H
(min)
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down mode
t
CK
=
∞
, CKE
≥
V
I H
(min)
, CLK
Input signals are stable
Precharge Standby Current in power-down mode
t
CK
= t
CK
(min), CKE
≤
V
I L
(max)
Precharge Standby Current in power-down mode
t
CK
=
∞
, CKE
≤
V
I L
(max)
, CLK
±
0.3V, Ta = 0 ~ 70°C)
-5.5
I
DD1
190
-6
185
-7
165
-8
145
Unit
Note
3,4
Symbol Min. Max. Min. Max. Min. Max. Min. Max.
I
DD2N
95
85
75
65
3
≤
V
IL
(max)
I
DD2NS
45
40
35
30
mA
I
DD2P
4
4
4
4
3
≤
V
IL
(max)
I
DD2PS
3.5
3.5
3.5
3.5
Active Standby Current in non power down mode
CKE
≥
V
I H
(min)
, t
CK
= t
CK(min)
(Both Bank Actioe)
Active Standby Current in power-down
CKE
≤
V
I L
(max)
, t
CK =
t
CK(min)
, CS
≥
V
IH(min)
(Both
Bank Active)
Operating Current (Page Burst, and All Bank activated)
t
CCD
= t
CCD(min)
, Outputs Open, Multi-bank interleave,
gapless data
Refresh Current
t
RC
≥
t
RC
(min)
(t
REF
= 64ms)
Self Refresh Current
CKE
I
DD3N
I
DD3P
85
6
75
6
65
6
55
6
3
I
DD4
195
185
175
165
4,5
I
DD5
I
DD6
185
175
165
155
3
≤
0.2V
4
4
4
4
Document:1G5-0160
Rev.1
Page 5
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
