VIS
Parameter
CAS
Latency
3
2
CLK to valid output delay
3
2
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
CLK to output in low - Z
CLK to output in H - Z
3
2
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
Data - in to ACT(REF) command
Data - in to precharge
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
CLK cycle time
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C V
DD
= 3.3V 0.3V, V
SS
= 0V)
VG36648041B
symbol
Min
t
ck3
t
ck2
t
Ac3
t
Ac2
t
CH
t
CL
t
CKS
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH
t
LZ
t
HZ
3
3
2
1
2
1
2
1
2
1
3
0
5
6
t
RRD
t
RCD
t
RP
t
RAS
t
RC
t
BDL
t
DAL
t
DPL
t
T
t
RSC
t
PDE
t
SRX
t
REF
14
20
20
40
60
1
1+ t
RP
1
1
2
2
1
64
10
120K
16
20
20
48
68
1
1+t
RP
1
1
2
2
1
64
10
120K
7
10
6
6
3
3
2
1
2
1
2
1
2
1
3
0
6
6
ns
ns
ns
ns
ns
CLK
CLK
CLK
ns
CLK
ns
CLK
ms
-7
Max
Min
8
10
6
6
-8
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Document : 1G5-0153
Rev.1
Page 7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
