VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
A.C. Characteristics (Ta = 0 ~ 70°C, V = V
= 3.3±0.3V , V = V
= 0V, unless otherwise noted)
DD
DDQ
SS
SSQ
Limits
Sym-
Parameter
bol
-6 *1
-7
-7L
-8H
Unit
Note
Min
Max
Min
7
Max
Min
Max
Min
8
Max
CLK cycle time
CL = 3
CL = 2
CL = 3
CL = 2
tCK3
tCK2
tAC3
tAC2
tCH
6
7.5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tck
ms
7.5
7.5
10
CLK to valid output
delay
5.4
6
5.4
6
5
6
6
6
*2
*2
CLK high pulse width
CLK low pulse width
CKE setup time
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.5
2.5
0
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
2.7
0
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
3
3
3
tCL
tCKS
tCKH
tAS
2
CKE hold time
1
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
2
tAH
1
tCMS
tCMH
tDS
2
1
2
tDH
1
Output data hold
time
CL = 3
CL = 2
tOH3
tOH2
tLZ
3
*2
*2
3
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
0
0
tHZ
5.4
2.5
60
42
18
15
12
12
1
5
2.7
63
42
20
15
14
14
1
5.4
2.7
67.5
45
20
20
15
15
1
3
6
tRC
70
50
20
20
20
20
1
ROW active time
tRAS
tRCD
tRP
100K
100K
100K
100K
RAS to CAS delay
Row precharge time
Row active to active delay
Data in to precharge
Transition time
tRRD
tDPL
tT
10
64
10
64
10
64
10
64
Mode reg. set cycle
Refresh time
tRSC
tREF
2
2
2
2
Notes
1. -6 grade is available only on 4MX16 option.
2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Document :1G5-0177
Rev.2
Page8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
