SCA103T Series
1.6
SPI Interface Timing Specifications
Parameter
Terminal CSB, SCK
Time from CSB (10%)
to SCK (90%)
Time from SCK (10%)
to CSB (90%)
Terminal SCK
SCK low time
SCK high time
Terminal MOSI, SCK
Time from changing MOSI
(10%, 90%) to SCK (90%).
Data setup time
Time from SCK (90%) to
changing MOSI (10%,90%).
Data hold time
Terminal MISO, CSB
Time from CSB (10%) to stable
MISO (10%, 90%).
Time from CSB (90%) to high
impedance state of
MISO.
Terminal MISO, SCK
Time from SCK (10%) to stable
MISO (10%, 90%).
Terminal CSB
Time between SPI cycles, CSB at high
level (90%)
When using SPI commands RDAX, RDAY,
RWTR: Time between SPI cycles, CSB at
high level (90%)
Conditions
Symbol
T
LS1
T
LS2
Min.
120
120
1
1
Typ.
Max.
Unit
ns
ns
µs
µs
Load
capacitance at
MISO < 2 nF
Load
capacitance at
MISO < 2 nF
T
CL
T
CH
T
SET
T
HOL
30
30
ns
ns
Load
capacitance at
MISO < 15 pF
Load
capacitance at
MISO < 15 pF
Load
capacitance at
MISO < 15 pF
T
VAL1
T
LZ
10
10
100
100
ns
ns
T
VAL2
100
ns
T
LH
TLH
15
150
µs
µs
T
LS1
CSB
SCK
T
CH
T
CL
T
LS2
T
LH
T
HOL
MOSI
T
VAL1
MISO
MSB out
MSB in
DATA in
T
SET
LSB in
T
VAL2
DATA out
LSB out
T
LZ
Figure 2.
Timing diagram for SPI communication
VTI Technologies Oy
www.vti.fi
Subject to changes
Doc.Nr. 8261700
5/19
Rev.A
VTI [ VTI TECHNOLOGIES ]
