SCA103T Series
1.7
Electrical Connection
If the SPI interface is not used SCK (pin1), MISO (pin3), MOSI (pin4) and CSB (pin7) must be left
floating. Self-test can be activated applying logic “1” (positive supply voltage level) to ST_1 or ST_2
pins (pins 10 or 9). Self-test must not be activated for both channels at the same time. If the ST
feature is not used, pins 9 and 10 must be left floating or connected to GND. Inclination signals are
provided from pins OUT_1 and OUT_2.
SCK
1
SCK
VDD
12 VDD
OUT_1
11 OUT_1
Ext_C_1 2
MISO
MISO
3
MOSI
MOSI
4
OUT_2
OUT_2
5
VSS
GND
6
10 ST_1/Test_in
ST_1
9
8
7
ST_2
ST_2
Ext_C_2
CSB
CSB
Figure 3.
No.
1
2
3
4
5
6
7
8
9
10
11
12
SCA103T electrical connection
Node
SCK
NC
MISO
MOSI
Out_2
GND
CSB
NC
ST_2
ST_1
Out_1
VDD
I/O
Input
Input
Output
Input
Output
Supply
Input
Input
Input
Input
Output
Supply
Description
Serial clock
No connect, left floating
Master in slave out; data output
Master out slave in; data input
Output 2 (Ch 2)
Ground
Chip select (active low)
No connect, left floating
Self test input for Ch 2
Self test input for Ch 1
Output 1(Ch 1)
Positive supply voltage (+5V DC)
1.8
Typical Performance Characteristics
Typical offset and sensitivity temperature dependencies of SCA103T are presented in following
diagrams. These results represent the typical performance of SCA103T components. The mean
value and 3 sigma limits (mean ± 3× standard deviation) and specification limits are presented in
following diagrams. The 3 sigma limits represents 99.73% of the SCA103T population.
VTI Technologies Oy
www.vti.fi
Subject to changes
Doc.Nr. 8261700
6/19
Rev.A
VTI [ VTI TECHNOLOGIES ]
