White Electronic Designs
FIGURE 4 – CAS LATENCY
T0
CLK#
CLK
COMMAND
READ
NOP
CL = 2
DQS
DQ
NOP
NOP
T1
T2
T2n
T3
T3n
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
W3E32M72S-XBX
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
14 13 12 11 10 9 8
01
11
7
6
5
4
3
2
1
0
Operating Mode
DS DLL
Extended Mode
Register (Ex)
E0
0
DLL
Enable
Disable
Drive Strength
Normal
Reduced
T0
CLK#
CLK
COMMAND
READ
T1
T2
T2n
T3
T3n
1
E1
NOP
CL = 2.5
NOP
NOP
0
1
DQS
DQ
E12 E11 E10 E9
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
E2
0
-
E1, E0
Valid
-
Operating Mode
Reserved
Reserved
Burst Length = 4 in the cases shown
Shown with nominal t
AC
and nominal t
DSDQ
DATA
TRANSITIONING DATA
DON'T CARE
0
-
0
-
0
-
0
-
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating t
RAS
(MIN).The user must not issue
another command to the same bank until the precharge
time (t
RP
) is completed.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
