White Electronic Designs
47. Random addressing changing: 50% of data changing at every transfer.
48. Random addressing changing: 100% of data changing at every transfer.
49. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t
RFC
has been satisfied.
50. I
CC2N
specifies the DQ, DQS, and DQM to be driven to a valid high or low logic
level. I
CC2Q
is similar to I
CC2F
except I
CC2Q
specifies the address and control inputs
to remain stable. Although I
CC2F
, I
CC2N
, and I
CC2Q
are similar, I
CC2F
is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.
W3E32M72S-XBX
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
