White Electronic Designs
Notes:
1. All voltages referenced to VSS.
2. Tests for AC timing, I
CC
, and electrical AC and DC characteristics may be conducted
at nominal reference / supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage range specified. ODT is disabled
for all measurements that are not ODT-specific.
3. Outputs measured with equivalent load:
V
TT =
V
CCQ
/2
25Ω
Output
(V
OUT
)
Reference
Point
W3HG128M64EEU-D4
ADVANCED*
15.
16.
17.
18.
19.
20.
4. AC timing and I
CC
tests may use a V
IL
-to-V
IH
swing of up to 1.0V in the test
environment and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The slew rate for the input signals used to test
the device is 1.0V/ns for signals in the range between V
IL
(AC) and V
IH
(AC). Slew
rates less than 1.0V/ns require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. There are two sets of values listed for Command/Address: t
ISa
, t
IHa
and t
ISb
, t
IHb
. The
t
ISa
, t
IHa
values (for reference only) are equivalent to the baseline values of t
ISb
, t
IHb
at V
REF
when the slew rate is 1V/ns. The baseline values, t
ISb
, t
IHb
, are the JEDEC
defined values, referenced from the logic trip points. t
ISb
is referenced from V
IH
(AC)
for a rising signal and V
IL
(AC) for a falling signal, while t
IHb
is referenced from V
IL
(DC) for a rising signal and V
IH
(DC) for a falling signal. If the Command/Address
slew rate is not equal to 1 V/ns, then the baseline values must be derated.
7. The values listed are for the differential DQS strobe (DQS and DQS#) with a
differential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values
listed:
t
DSa.
t
DHa and
t
DSb,
t
DHb. The
t
DSa,
t
DHa values (for reference only) are
equivalent to the baseline values of
t
DSb,
t
DHb at V
REF
when the slew rate is 2
V/ns, differentially. The baseline values,
t
DSb,
t
DHb, are the JEDEC-defined values,
referenced from the logic trip points.
t
DSb is referenced from V
IH
(AC) for a rising
signal and V
IL
(AC) for a falling signal, while
t
DSb is referenced from V
IL
(DC) for a
rising signal and V
IH
(DC) for a falling signal. If the differential DQS slew rate is not
equal to 2 V/ns, then the baseline values must be derated. If the DQS differential
strobe feature is not enabled, then the DQS strobe is single-ended, the baseline
values not applicable, and timing is not referenced to the logic trip points. Single-
ended DQS data timing is referenced to DQS crossing V
REF
.
t
8. HZ and
t
LZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (
t
HZ) or begins driving (
t
LZ).
9. This maximum value is derived from the referenced test load.
t
HZ (MAX) will prevail
over
t
DQSCK (MAX) +
t
RPST (MAX) condition.
10.
t
LZ (MIN) will prevail over a
t
DQSCK (MIN) +
t
RPRE (MAX) condition
11. The intent of the "Don’t Care" state after completion of the postamble is the DQS-
driven signal should either be high, low or High-Z and that any signal transition
within the input switching region must follow valid input requirements. That is if DQS
transitions high (above V
IH
DC(min) then it must not transition low (below V
IH
(DC)
prior to
t
DQSH(min).
12. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on
t
DQSS.
14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to an
average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a
REFRESH command must be asserted at least once every 70.3µs or
t
RFC (MAX).
March 2006
Rev. 0
10
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
To ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands
must be issued every 64ms.
Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with
DQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured
differentially).
The data valid window is derived by achieving other specifications -
t
HP. (
t
CK/2),
t
DQSQ, and
t
QH (
t
QH =
t
HP -
t
QHS). The data valid window derates in direct
proportion to the clock duty cycle and a practical data valid window can be derived.
READs and WRITEs with auto precharge are allowed to be issued before
t
RAS(MIN) is satisfied since
t
RAS lockout feature is supported in DDR2 SDRAM.
V
IL
/V
IH
DDR2 overshoot/undershoot.
t
DAL = (nWR) + (
t
RP/
t
CK). Each of these terms, if not already an integer, should be
rounded up to the next integer.
t
CK refers to the application clock period; nWR refers
with
t
WR programmed to four clocks would have
t
DAL = 4 + (15ns/3.75ns) clocks =
4 + (4) clocks = 8 clocks.
The minimum internal READ to PRECHARGE time. This is the time from the last
4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit
prefetch is when the READ command internally latches the READ so that data will
output CL later. This parameter is only applicable when
t
RTP/(2x
t
CK) > 1, such as
frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/ (2x
t
CK) ≤ 1, then
equation AL + BL/2 applies. tRAS (MIN) also has to be satisfied as well. The DDR2
SDRAM will automatically delay the internal PRECHARGE command until
t
RAS
(MIN) has been satisfied.
Operating frequency is only allowed to change during self refresh mode, precharge
power-down mode, and system reset condition.
t
DAL = (nWR) + (
t
RP/
t
CK): For each of the terms above, if not already an integer,
round to the next highest integer.
t
CK refers to the application clock period;
AC Operation Condition Notes: nWR refers to the
t
WR parameter stored in the
MR[11,10,9]. Example: For -533Mb/s at
t
CK = 3.75 ns with
t
WR programmed to four
clocks.
t
DAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.
ODT turn-off time
t
AOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time
t
AOF (MAX) is when the bus is in high-Z. Both are measured from
t
AOFD.
This parameter has a two clock minimum requirement at any
t
CK.
t
DELAY is calculated from
t
IS +
t
CK +
t
IH so that CKE registration LOW is
guaranteed prior to CK, CK# being removed in a system RESET condition.
t
ISXR is equal to
t
IS and is used for CKE setup time during self refresh exit.
No more than 4 bank ACTIVE commands may be issued in a given
t
FAW(min)
period.
t
RRD(min) restriction still applies. The
t
FAW(min) parameter applies to all 8
bank DDR2 devices, regardless of the number of banks already open or closed.
t
RPA timing applies when the PRECHARGE(ALL) command is issued, regardless
of the number of banks already open or closed. If a single-bank PRECHARGE
command is issued,
t
RP timing applies.
t
RPA(MIN) applies to all 8-bank DDR2
devices.
Value is minimum pulse width, not the number of clock registrations.
This is applicable to Read cycles only. Write cycles generally require additional time
due to
t
WR during auto precharge.
t
CKE (MIN) of 3 clocks means CKE must be registered on three consecutive
positive clock edges. CKE must remain at the valid input level the entire time it takes
to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of
t
IS + 2 x
t
CK +
t
IH.
This parameter is not referenced to a specific voltage level, but specified when the
device output is no longer driving (
t
RPST) or beginning to drive (
t
RPRE).
When DQS is used single-ended, the minimum limit is reduced by 100ps.
The half-clock of
t
AOFD's 2.5
t
CK assumes a 50/50 clock duty cycle. This half-clock
value must be derated by the amount of half-clock duty cycle error. For example, if
the clock duty cycle was 47/53,
t
AOFD would actually be 2.5 - 0.03, or 2.47 for
t
AOF
(MIN) and 2.5 + 0.03 or 2.53 for
t
AOF (MAX).
The clock’s
t
CK
AVG
is the average clock over any 200 consecutive clocks and
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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